1. Field of the Invention
The present invention relates to a system for determining values of data forming a data frame periodically repeating in a digital signal.
2. Description of Related Art
A typical digital tester tests a digital electronic device under test (DUT) by causing the DUT to produce one or more digital output signals and then periodically sampling each digital output signal to produce sample data representing values of data the digital output signal conveys. The tester then compares the sample data to data values the digital output signal is expected to convey to determine whether the DUT is operating properly.
FIG. 1 illustrates a portion of a prior art test system including a digitizer 10 for sampling the digital output signal (OUT) of a DUT 12 on successive edges of a clock signal (CLOCK1) to produce sample data (DATA) supplied to a data processor 13 which then may compare the sample data to expected data values. A second clock signal (CLOCK2) controls the timing of state changes in the OUT signal.
FIG. 2 is a timing diagram illustrating the OUT, CLOCK1 and CLOCK2 signals and the data output (DATA) produced by digitizer 10. The OUT signal may change state only in response to leading edges of the CLOCK2 signal. In this example the OUT signal conveys a data bit every PD seconds, the period of the CLOCK2 signal, and repeats a 10-bit data frame (1010101100) every PF seconds. With the CLOCK1 signal also having a period PD matching the length of one data cycle of the OUT signal, digitizer 10 can digitize the OUT signal in response to leading edges of ten successive pulses of the CLOCK1 signal to produce a sequence of ten output DATA bits indicating the 10-bit data pattern forming each data frame of the OUT signal.
Digitizer 10 may implement equivalent time sampling when it is not capable of digitizing the OUT signal at a frequency as high as 1/PD. As illustrated in FIG. 3, the CLOCK1 signal period is increased to the sum of data period PD and an integer multiple N of frame period PF. Ten successive CLOCK1 signal pulses will cause digitizer 10 to produce the same 10-bit DATA signal pattern as it would have produced had the CLOCK1 signal had a period of PD as in FIG. 2.
When using digitizer 10 to produce the DATA stream representing the OUT signal, it is necessary to adjust the CLOCK1 signal phase so that it samples the OUT signal at a point during each data cycle when the data bit is valid. However when the CLOCK1 and CLOCK2 signals are not coherent (i.e. not derived from the same source), the phase relationship between the OUT and CLOCK1 signals is indeterminate. Any device controlling the CLOCK1 signal phase will be unable to determine how to adjust the CLOCK1 signal phase because it will have no knowledge of the phase of the OUT signal. When the CLOCK1 and CLOCK2 signals are not closely synchronized, digitizer 10 may sample the OUT signal at a time when the OUT signal is undergoing a rising or falling edge transition and hence may produce an erroneous DATA output. Also in very high frequency applications a digitizer may not be able to sample the OUT signal with sufficient timing resolution.
What is needed is a system for recovering a repetitive data stream from a digital signal that does not require knowledge of the phase of the digital signal and that does not use a digitizer to sample the digital signal.
In accordance with the invention, a system for ascertaining a value of each bit of a data frame of nominal duration PF periodically repeating in a digital signal and having a known data period PD produced by a device under test (DUT) includes a clock signal generator (CSG), a time interval analyzer (TIA) and a computer. The TIA measures time intervals TR(k) and TF(k) between a reference time and times of subsequent rising and falling edges of the digital signal measured in response to each kth pulse of a periodic arming signal (ARM) produced by the CSG. The period PA of the arming signal is:
PA=NPF+DT 
where N is any integer greater than 0 and DT is a xe2x80x9cdelta timexe2x80x9d interval substantially smaller than PD. With the ARM signal period set in this fashion, each successive ARM signal edge will fall at a different time relative to the start of an OUT signal frame. After many cycles of the ARM signal, the generated TR and TF data will include several measurements of the timing of each rising and falling edge of the data frame relative to the reference time. In accordance with the invention, the value of data conveyed in the data frame is determined from the generated TR and TF data.
It is accordingly an object of the invention to ascertain a value of all bits of a data stream conveyed in a digital signal produced by a DUT when the phase of the digital signal is indeterminate.
The claims portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.